VHDL: OR-ing bits of a vector together
or_reduce
is what you want, and it is available in std_logic_misc
. Supported by both A and X for FPGAs.
Verilog has a convenient "reduction operator" that does exactly what you're asking for: |example[23:0]
gives the result of OR'ing all the bits of the example
vector.
Unfortunately VHDL doesn't have this operator. According to the comp.lang.vhdl FAQ, though
There is no predefined VHDL operator to perform a reduction operation on all bits of vector (e.g., to "or" all bits of a vector). However, the reduction operators can be easily implemented:
[skipping an example that doesn't handle 'X' and 'Z' values]
function or_reduce( V: std_logic_vector ) return std_ulogic is variable result: std_ulogic; begin for i in V'range loop if i = V'left then result := V(i); else result := result OR V(i); end if; exit when result = '1'; end loop; return result; end or_reduce; ... b <= or_reduce( b_vec );