What does "net" stand for in Verilog?

A net is such a data type, where you don't use it for storing values. They represent physical connections. You can think of wire as a net data type.
You can see more on nets here.

A net is short for network, and a network is a group of devices that share a common connection, a wire in most cases here. Net's represent connections as opposed to variables which hold values. I wrote a short article to explain why Verilog has nets.