What's the difference between parenthesis $() and curly bracket ${} syntax in Makefile?

There's no difference – they mean exactly the same (in GNU Make and in POSIX make).

I think that $(round brackets) look tidier, but that's just personal preference.

(Other answers point to the relevant sections of the GNU Make documentation, and note that you shouldn't mix the syntaxes within a single expression)

The Basics of Variable References section from the GNU make documentation state no differences:

To substitute a variable's value, write a dollar sign followed by the name of the variable in parentheses or braces: either $(foo) or ${foo} is a valid reference to the variable foo.

As already correctly pointed out, there is no difference but be be wary not to mix the two kind of delimiters as it can lead to cryptic errors like in the GNU make example by unomadh.

From the GNU make manual on the Function Call Syntax (emphasis mine):

[…] If the arguments themselves contain other function calls or variable references, it is wisest to use the same kind of delimiters for all the references; write $(subst a,b,$(x)), not $(subst a,b,${x}). This is because it is clearer, and because only one type of delimiter is matched to find the end of the reference.